By Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech
Discovering new fabrics for copper/low-k interconnects is important to the continued improvement of machine chips. whereas copper/low-k interconnects have served good, making an allowance for the production of extremely huge Scale Integration (ULSI) units which mix over 1000000000 transistors onto a unmarried chip, the elevated resistance and RC-delay on the smaller scale has turn into a significant component affecting chip functionality.
Advanced Interconnects for ULSI Technology is devoted to the fabrics and techniques that can be compatible replacements. It covers a huge variety of themes, from actual ideas to layout, fabrication, characterization, and alertness of recent fabrics for nano-interconnects, and discusses:
- Interconnect features, characterisations, electric homes and wiring specifications
- Low-k fabrics: basics, advances and mechanical homes
- Conductive layers and obstacles
- Integration and reliability together with mechanical reliability, electromigration and electric breakdown
- New techniques together with 3D, optical, instant interchip, and carbon-based interconnects
Intended for postgraduate scholars and researchers, in academia and undefined, this ebook presents a serious assessment of the allowing know-how on the center of the longer term improvement of computing device chips.
Chapter 1 Low?k fabrics: fresh Advances (pages 1–33): Geraud Dubois and Willi Volksen
Chapter 2 Ultra?Low?k through CVD: Deposition and Curing (pages 35–77): Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov
Chapter three Plasma Processing of Low?k Dielectrics (pages 79–128): Hualiang Shi, Denis Shamiryan, Jean?Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov
Chapter four rainy fresh functions in Porous Low?k Patterning procedures (pages 129–171): Quoc Toan Le, man Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov
Chapter five Copper Electroplating for On?Chip Metallization (pages 173–191): Valery M. Dubin
Chapter 6 Diffusion boundaries (pages 193–234): Michael Hecker and Rene Hubner
Chapter 7 technique Integration of Interconnects (pages 235–265): Sridhar Balakrishnan, Ruth mind and Larry Zhao
Chapter eight Chemical Mechanical Planarization for Cu–Low?k Integration (pages 267–289): Gautam Banerjee
Chapter nine Scaling and Microstructure results on Electromigration Reliability for Cu Interconnects (pages 291–337): Chao?Kun Hu, Rene Hubner, Lijuan Zhang, Meike Hauschildt and Paul S. Ho
Chapter 10 Mechanical Reliability of Low?k Dielectrics (pages 339–367): Kris Vanstreels, Han Li and Joost J. Vlassak
Chapter eleven electric Breakdown in complicated Interconnect Dielectrics (pages 369–434): Ennis T. Ogawa and Oliver Aubel
Chapter 12 3D Interconnect know-how (pages 435–490): John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
Chapter thirteen Carbon Nanotubes for Interconnects (pages 491–502): Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano
Chapter 14 Optical Interconnects (pages 503–542): Wim Bogaerts
Chapter 15 instant Interchip Interconnects (pages 543–563): Takamaro Kikkawa
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Extra resources for Advanced Interconnects for ULSI Technology
1), plasma-enhanced chemical vapor deposition (PECVD) has been the method of choice for depositing silicon dioxide (SiO2), fluorine-doped oxides (F-SiO2), carbon-doped oxides (SiCOH: elementally descriptive but not representing the stoichiometry) and porous carbon-doped oxides (p-SiCOH). 7) technology nodes in 2004 and 2006, respectively. 1). Interestingly, the real IBM technology node/dielectric constant relationship differs significantly from the targets proposed by the NTRS in 1997. This shows the danger of predicting dielectric targets based solely on engineering designs when new materials are not readily available.
One novel integration approach combines both hybrid integration (useful for minimizing ILD damage at the trench level) and a new concept referred to as ‘effective porogen control’ (ECB) . e. the via level, to less than 70 %. The remaining porogen effectively increases the carbon content of this layer protecting the via level. The remaining porogen is partially removed during the plasma processing steps (trench level), followed by a thermal cure after a complete DD build. 4 Material Advances to Overcome Current Limitations In the search for improved mechanical properties of highly porous materials, two candidates have emerged over the past few years.
Barrier layer deposition and 2. Cu plating. The barrier is generally a bilayer consisting of a metal nitride and a barrier metal to protect the ILD from Cu migration/penetration and typical examples are TaN/Ta and TiN/Ti. The function of the metal nitride is to provide excellent adhesion to the ILD, whereas the barrier metal provides an optimum interface to the Cu. For maximum effectiveness, this barrier layer needs to be continuous and without defects and pinholes. 3 (h) [48, 49]. However, as line and via dimensions shrink in accordance with future technology nodes, thinner barrier layers are needed to maintain or improve electrical performance.
Advanced Interconnects for ULSI Technology by Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech